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TQS Reliability Report # 00-08
TQ8223 Device Qualification
Abstract
This report summarizes the reliability testing that has been performed to qualify the TQ8223 product. The SC5068 is a Superset of the TQ8223 and was previously qualified. The TQ8213, which is also packaged in a 208 BGA, was used as an additional lot for dimensional qualification.
TQ8223 and SC5068 Both of these parts are fabricated on TriQuint's 0.6m E/D MESFET GaAs process and are packaged in a 208 BGA package. Tests, test sample size and failure criteria were defined from TriQuint' Specification REL.021 (Policy and Procedure for Reliability Qualifications of ICs). Tests s outlined in this procedure follow the JEDEC Standard Number 26-A or MIL-STD-883 when applicable.
For further information please contact: TriQuint Semiconductor
2300 N.E. Brookwood Parkway Hillsboro, OR 97124 Phone: (503) 615-9000 FAX: (503) 615-8900
Reliability Test Report
08/01/00
TQS Reliability Report # 00-08
TQ8223 Device Product Qualification
Reliability Test Report
08/01/00
Process Description
TriQuint' QEDA2 process is a Gallium Arsenide (GaAs) semiconductor process fabricated at TriQuint' s s Hillsboro, Oregon facility
Product Description
The TQ8223 is a TriQuint standard product, which is similar to the SC5068. Both parts are identical except for added circuitry in the SC5068 containing key customer intellectual property. The SC5068 was chosen to qualify both parts since it is a superset of the TQ8223. The TQ8223 and SC5068 are multi-configuration SONET/SDH OC48/STM16 CDR/DEMUX that regenerate and re-time serial 2.48832 Gb/s data. They recover the 2.48832 GHz clock from the data stream and frequency divide it to generate control signals and clocks used to perform the demultiplexing function. The TQ8223 and SC5068 operate in one of three different time-division demultiplexing modes, making it extremely flexible for telecom, ATM and networking applications. The serial 2.48832 Gb/s data stream can be demultiplexed into either an 8-bit wide 311.04 MHz TTL data bus, a 16-bit wide 155.52 MHz TTL data bus, or a 32-bit wide 77.76 MHz TTL data bus. Internal data inversion is also available. The device generates byte-wise parity check bits for the demultiplexed data and provides associated clock outputs for the different modes. Parity checking is not required for normal device operation. The TQ8223 and SC5068 provide added flexibility through a selectable internal/external Voltage Controlled Oscillator (VCO) as well as a selectable internal Phase Locked Loop (PLL). If an external high frequency clock is utilized, a single-ended or differential AC coupled clock may be used. The internal PLL contains a NRZ phase detector which enables it to adjust the phase of the internal clock such that sampling of the incoming data stream occurs in the middle of the data eye. An offset control allows adjustment of 128pS around this nominal position. Operating from a single +5V supply, the TQ8223 and SC5068 are fully compliant with SONET/SDH jitter tolerance and transfer specifications. A TTL level LOCK signal is supplied to indicate when the frequency difference between the internal 38.88 MHz clock and the external 38.88 MHz clock is less than 488 ppm.
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TQS Reliability Report # 00-08
TQ8223 Device Product Qualification
Reliability Test Report
08/01/00
Test Plan:
Table 1 lists the tests that were performed on the SC5068.
Table 1. Device Qualification Test Plan.
Item #
1
Test Name
Autoclave
Purpose
Determine the effect of temp, humidity & pressure on the device over time, unbiased Material Thermal Mismatch Determine the effect of bias and temperature on the device over an extended period of time
Specification - Method or Conditions
JEDEC A102, Condition C 121oC, 100% RH, 15 PSI for 96 Hours
Sample Size
1 Lot 45/0 1 Lot 45/0 1 Lot 45/0 1 Lot 3/0 2 Lots 2 Lots 2 Lots
2
Thermal Cycle (Air to Air)
JESD22A-104-A similar to Condition B
-40oC to +125oC for 1,000 Cycles MIL-STD-883D, Method 1015.8 VDD = 5.0 V, Junction Temp 150oC for 1000 Hours JESD22-A114A (HBM) >1,000 V External VI Inspection
3
HTOL Lifetest
4 5
ESD Stress Mechanical
Determine the sensitivity of the device to levels of ESD Verify the mechanical capabilities of the product
JEDEC Std.22 M-B101 Physical Dimensions JEDEC Std.22 M-B100
Marking Permanency JEDEC Std 22, M-B107
6
Moisture Level Sensitivity
Determine/Classify the moisture sensitivity of plastic surface mount IC' s
Moisture Level Sensitivity J-Std-020 Level 2
1 Lot
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TQS Reliability Report # 00-08
TQ8223 Device Product Qualification
Reliability Test Report
08/01/00
Summary of Results:
Table 2 lists the status and results of the qualification testing for SC5068.
Table 2. Qualification Test Results Summary.
Sample Size 1 Lot 45 (0) 1 Lot 45 (0) 1Lot 45 (0) 1 Lot 3 2 Lots 15 (0)
Test Description Autoclave Temperature Cycle Bias Life test ESD Sensitivity HBM Physical Dimensions
Status
Complete Complete Complete Complete Complete
Lot #1
45(0) Passed 45(0) Passed 50(0) Passed Passed at 1,000V Passed
Lot #2
Mark Permanency
2 Lots 25 (1)
Complete
Passed
Passed Second lot of material was TQ-8213 Passed Second lot of material was TQ-8213
Moisture Sensitivity Level Testing
1 Lot
Complete
Passed Level 2
Summary:
Moisture sensitivity testing has been completed, with level 2 rating established. All other testing was successfully completed. Based in the fact that the SC5068 has successfully completed the required qualification tests, the TQ8223 is qualified by similarity.
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TQS Reliability Report # 00-08
TQ8223 Device Product Qualification
Reliability Test Report
08/01/00
Appendix A
SC5068 Burn In Schematic
+5V
VDD A B C D E F PECL Inputs TTL Inputs Analog1 Inputs Analog2 Inputs Analog3 Inputs Analog4 Inputs PECL Outputs TTL Outputs G H
Analog Outputs
I
SC5068
VEE
PECL Inputs VDD 820 A 1.5K 510
TTL Inputs
Analog1 Inputs VDD 330 C 240
Analog2 Inputs VDD 240 D
B
Analog3 Inputs
Analog4 Inputs
PECL Outputs
E 1.5K 10K
F G 330
TTL Outputs VDD 1.5K H 1.5K
Analog Outputs
VDD 240 I
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